6502 instruction set

Here's the instruction set of the original NMOS version of the 6502 CPU, in a minimal and extensive table. I made these tables to help see quickly what's going on when manually disassembling and/or debugging code. The 2nd table is inspired by the 6502 CPU table on http://pastraiser.com/. I like the colour scheme used, and how the information is presented, so I made my table in that style with some changes to make it prettier and there were a few errors in that table so I remade it though there was 1 error still there. After fixing that quite a while ago (2014), hopefully it is without errors. But that there was still one mistake made me think that perhaps a good idea would be to make such tables from the output of a disassembler/emulator, which would make it far less likely that errors remain...

All 6502 NMOS manufacturer documented instructions

00 BRK

01 ORA (zp,X)

05 ORA zp

06 ASL zp

08 PHP

09 ORA #n

0A ASL A

0D ORA abs

0E ASL abs

10 BPL rel

11 ORA (zp),Y

15 ORA zp,X

16 ASL zp,X

18 CLC

19 ORA abs,Y

1D ORA abs,X

1E ASL abs,X

20 JSR abs

21 AND (zp,X)

24 BIT zp

25 AND zp

26 ROL zp

28 PLP

29 AND #n

2A ROL A

2C BIT abs

2D AND abs

2E ROL abs

30 BMI rel

31 AND (zp),Y

35 AND zp,X

36 ROL zp,X

38 SEC

39 AND abs,Y

3D AND abs,X

3E ROL abs,X

40 RTI

41 EOR (zp,X)

45 EOR zp

46 LSR zp

48 PHA

49 EOR #n

4A LSR A

4C JMP abs

4D EOR abs

4E LSR abs

50 BVC rel

51 EOR (zp),Y

55 EOR zp,X

56 LSR zp,X

58 CLI

59 EOR abs,Y

5D EOR abs,X

5E LSR abs,X

60 RTS

61 ADC (zp,X)

65 ADC zp

66 ROR zp

68 PLA

69 ADC #n

6A ROR A

6C JMP (abs)

6D ADC abs

6E ROR abs

70 BVS rel

71 ADC (zp),Y

75 ADC zp,X

76 ROR zp,X

78 SEI

79 ADC abs,Y

7D ADC abs,X

7E ROR abs,X

81 STA (zp,X)

84 STY zp

85 STA zp

86 STX zp

88 DEY

8A TXA

8C STY abs

8D STA abs

8E STX abs

90 BCC rel

91 STA (zp),Y

94 STY zp,X

95 STA zp,X

96 STX zp,Y

98 TYA

99 STA abs,Y

9A TXS

9D STA abs,X

A0 LDY #n

A1 LDA (zp,X)

A2 LDX #n

A4 LDY zp

A5 LDA zp

A6 LDX zp

A8 TAY

A9 LDA #n

AA TAX

AC LDY abs

AD LDA abs

AE LDX abs

B0 BCS rel

B1 LDA (zp),Y

B4 LDY zp,X

B5 LDA zp,X

B6 LDX zp,Y

B8 CLV

B9 LDA abs,Y

BA TSX

BC LDY abs,X

BD LDA abs,X

BE LDX abs,Y

C0 CPY #n

C1 CMP (zp,X)

C4 CPY zp

C5 CMP zp

C6 DEC zp

C8 INY

C9 CMP #n

CA DEX

CC CPY abs

CD CMP abs

CE DEC abs

D0 BNE rel

D1 CMP (zp),Y

D5 CMP zp,X

D6 DEC zp,X

D8 CLD

D9 CMP abs,Y

DD CMP abs,X

DE DEC abs,X

E0 CPX #n

E1 SBC (zp,X)

E4 CPX zp

E5 SBC zp

E6 INC zp

E8 INX

E9 SBC #n

EA NOP

EC CPX abs

ED SBC abs

EE INC abs

F0 BEQ rel

F1 SBC (zp),Y

F5 SBC zp,X

F6 INC zp,X

F8 SED

F9 SBC abs,Y

FD SBC abs,X

FE INC abs,X

All 6502 NMOS manufacturer documented instructions, more detailed information per instruction

	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x	00 BRK 1B 7c -----V	ORA (zp,X) 2 6 NZ----				ORA zp 2 3 NZ----	ASL zp 2 5 NZC---		PHP 1 3 ------	ORA # 2 2 NZ----	ASL A 1 2 NZC---			ORA abs 3 4 NZ----	ASL abs 3 6 NZC---
1x	BPL r8 2 3+/2 ------	ORA (zp),Y 2 5+ NZ----				ORA zp,X 2 4 NZ----	ASL zp,X 2 6 NZC---		CLC 1 2 --C---	ORA abs,Y 3 4+ NZ----				ORA abs,X 3 4+ NZ----	ASL abs,X 3 7 NZC---
2x	JSR abs 3 6 ------	AND (zp,X) 2 6 NZ----			BIT zp 2 3 NZ---V	AND zp 2 3 NZ----	ROL zp 2 5 NZC---		PLP 1 4 NZCIDV	AND # 2 2 NZ----	ROL A 1 2 NZC---		BIT abs 3 4 NZ---V	AND abs 3 4 NZ----	ROL abs 3 6 NZC---
3x	BMI r8 2 3+/2 ------	AND (zp),Y 2 5+ NZ----				AND zp,X 2 4 NZ----	ROL zp,X 2 6 NZC---		SEC 1 2 --C---	AND abs,Y 3 4+ NZ----				AND abs,X 3 4+ NZ----	ROL abs,X 3 7 NZC---
4x	RTI 1 6 NZCIDV	EOR (zp,X) 2 6 NZ----				EOR zp 2 3 NZ----	LSR zp 2 5 NZC---		PHA 1 3 ------	EOR # 2 2 NZ----	LSR A 1 2 NZC---		JMP abs 3 3 ------	EOR abs 3 4 NZ----	LSR abs 3 6 NZC---
5x	BVC r8 2 3+/2 ------	EOR (zp),Y 2 5+ NZ----				EOR zp,X 2 4 NZ----	LSR zp,X 2 6 NZC---		CLI 1 2 ---I--	EOR abs,Y 3 4+ NZ----				EOR abs,X 3 4+ NZ----	LSR abs,X 3 7 NZC---
6x	RTS 1 6 ------	ADC (zp,X) 2 6 NZC--V				ADC zp 2 3 NZC--V	ROR zp 2 5 NZC---		PLA 1 4 ------	ADC # 2 2 NZC--V	ROR A 1 2 NZC---		JMP (abs) 3 5 ------	ADC abs 3 4 NZC--V	ROR abs 3 6 NZC---
7x	BVS r8 2 3+/2 ------	ADC (zp),Y 2 5+ NZC--V				ADC zp,X 2 4 NZC--V	ROR zp,X 2 6 NZC---		SEI 1 2 ---I--	ADC abs,Y 3 4+ NZC--V				ADC abs,X 3 4+ NZC--V	ROR abs,X 3 7 NZC---
8x		STA (zp,X) 2 6 ------			STY zp 2 3 ------	STA zp 2 3 ------	STX zp 2 3 ------		DEY 1 2 NZ----		TXA 1 2 NZ----		STY abs 3 4 ------	STA abs 3 4 ------	STX abs 3 4 ------
9x	BCC r8 2 3+/2 ------	STA (zp),Y 2 6 ------			STY zp,X 2 4 ------	STA zp,X 2 4 ------	STX zp,Y 2 4 ------		TYA 1 2 NZ----	STA abs,Y 3 5 ------	TXS 1 2 ------			STA abs,X 3 5 ------
Ax	LDY # 2 2 NZ----	LDA (zp,X) 2 6 NZ----	LDX # 2 2 NZ----		LDY zp 2 3 NZ----	LDA zp 2 3 NZ----	LDX zp 2 3 NZ----		TAY 1 2 NZ----	LDA # 2 2 NZ----	TAX 1 2 NZ----		LDY abs 3 4 NZ----	LDA abs 3 4 NZ----	LDX abs 3 4 NZ----
Bx	BCS r8 2 3+/2 ------	LDA (zp),Y 2 5+ NZ----			LDY zp,X 2 4 NZ----	LDA zp,X 2 4 NZ----	LDX zp,Y 2 4 NZ----		CLV 1 2 -----V	LDA abs,Y 3 4+ NZ----	TSX 1 2 NZ----		LDY abs,X 3 4+ NZ----	LDA abs,X 3 4+ NZ----	LDX abs,Y 3 4+ NZ----
Cx	CPY # 2 2 NZC---	CMP (zp,X) 2 6 NZC---			CPY zp 2 3 NZC---	CMP zp 2 3 NZC---	DEC zp 2 5 NZ----		INY 1 2 NZ----	CMP # 2 2 NZC---	DEX 1 2 NZ----		CPY abs 3 4 NZC---	CMP abs 3 4 NZC---	DEC abs 3 6 NZ----
Dx	BNE r8 2 3+/2 ------	CMP (zp),Y 2 5+ NZC---				CMP zp,X 2 4 NZC---	DEC zp,X 2 6 NZ----		CLD 1 2 ----D-	CMP abs,Y 3 4+ NZC---				CMP abs,X 3 4+ NZC---	DEC abs,X 3 7 NZ----
Ex	CPX # 2 2 NZC---	SBC (zp,X) 2 6 NZC--V			CPX zp 2 3 NZC---	SBC zp 2 3 NZC--V	INC zp 2 5 NZ----		INX 1 2 NZ----	SBC # 2 2 NZC--V	NOP 1 2 ------		CPX abs 3 4 NZC---	SBC abs 3 4 NZC--V	INC abs 3 6 NZ----
Fx	BEQ r8 2 3+/2 ------	SBC (zp),Y 2 5+ NZC--V				SBC zp,X 2 4 NZC--V	INC zp,X 2 6 NZ----		SED 1 2 ----D-	SBC abs,Y 3 4+ NZC--V				SBC abs,X 3 4+ NZC--V	INC abs,X 3 7 NZ----

		Misc/control instructions
		Jumps/branches/calls
		Load/store/transfer instructions
		Arithmetic/logical instructions
		Shift/rotation instructions

Length in bytes →

INS zp
2 3
NZCIDV

← Instruction mnemonic and adressing mode
← Duration in cycles
← Flags affected

Adressing modes:
- zp = zero page (00-FF)
- abs = absolute (0000 - FFFF)
- #= immediate (byte value)
- ( ) = indirect = the address used is contained in the memory indicated
- ,X and ,Y are indexed adressing, address is calculated by adding the value of X or Y respectively.

Duration of instructions:
- The duration of conditional branches is 2 cycles when a branch is not taken, 3 cycles when a branch is taken and 4 cycles when a branch is taken and in doing so crosses a 256 byte page boundary. This is indicated with a +.
- The duration of instructions with indexed addressing is one cycle longer, when the target ('offset' or indirect, + index) address crosses a 256 byte page compared to the initial address ('offset' or indirect). This is indicated with a +.