6502 instruction set, illegal opcodes

As an aid to manual disassembling that I sometimes do, I made the following tables of the instruction set of the original NMOS version of the 6502 CPU, including the so-called 'illegal' instructions, i.e. the side effects of how the CPU was implemented. These give some useful operations, but the downside of using such instructions is that they don't work on the 65C02. There are also warnings in various places that they may not work on 6502 CPUs made by other manufacturers (the 6502 was made by MOS, Rockwell, Synertek, perhaps others). From the few tests that I did test it seems the other manufacturers used the original templates to fabricate their (licenced!) 6502, so this could be a non-issue except for modified CPUs such as Commodore used in some computers (but these are not called a 6502...).

00-07:	00 BRK	01 ORA (zp,X)	02 * HALT	03 * ASL-ORA (zp,X)	04 * NOP zp	05 ORA zp	06 ASL zp	07 * ASL-ORA zp
08-0F	08 PHP	09 ORA #n	0A ASL A	0B * AND #n/MOV b7->Cy	0C * NOP abs	0D ORA abs	0E ASL abs	0F * ASL-ORA abs
10-17	10 BPL rel	11 ORA (zp),Y	12 HALT	13 ASL-ORA (zp),Y	14 NOP zp	15 ORA zp,X	16 ASL zp,X	17 ASL-ORA abs,X
18-1F	18 CLC	19 ORA abs,Y	1A NOP	1B ASL-ORA abs,Y	1C NOP abs	1D ORA abs,X	1E ASL abs,X	1F ASL-ORA abs,X
20-27	20 JSR abs	21 AND (zp,X)	22 HALT	23 ROL-AND (zp,X)	24 BIT zp	25 AND zp	26 ROL zp	27 ROL-AND zp
28-2F	28 PLP	29 AND #n	2A ROL A	2B AND #n-MOV b7->Cy	2C BIT abs	2D AND abs	2E ROL abs	2F ROL-AND abs
30-37	30 BMI rel	31 AND (zp),Y	32 HALT	33 ROL-AND (zp),Y	34 NOP zp	35 AND zp,X	36 ROL zp,X	37 ROL-AND zp,X
38-3F	38 SEC	39 AND abs,Y	3A NOP	3B ROL-AND abs,Y	3C NOP abs	3D AND abs,X	3E ROL abs,X	3F ROL-AND abs,X
40-47	40 RTI	41 EOR (zp,X)	42 HALT	43 LSR-EOR (zp,X)	44 NOP zp	45 EOR zp	46 LSR zp	47 LSR-EOR zp
48-4F	48 PHA	49 EOR #n	4A LSR A	4B AND #n-LSR A	4C JMP abs	4D EOR abs	4E LSR abs	4F LSR-EOR abs
50-57	50 BVC rel	51 EOR (zp),Y	52 HALT	53 LSR-EOR (zp),Y	54 NOP zp	55 EOR zp,X	56 LSR zp,X	57 LSR-EOR abs,X
58-5F	58 CLI	59 EOR abs,Y	5A NOP	5B LSR-EOR abs,Y	5C NOP abs	5D EOR abs,X	5E LSR abs,X	5F LSR-EOR abs,X
60-67	60 RTS	61 ADC (zp,X)	62 HALT	63 ROR-ADC (zp,X)	64 NOP zp	65 ADC zp	66 ROR zp	67 ROR-ADC zp
68-6F	68 PLA	69 ADC #n	6A ROR A	6B AND #n-ROR A	6C JMP (abs)	6D ADC abs	6E ROR abs	6F ROR-ADC abs
70-77	70 BVS rel	71 ADC (zp),Y	72 HALT	73 ROR-ADC (zp),Y	74 NOP zp	75 ADC zp,X	76 ROR zp,X	77 ROR-ADC abs,X
78-7F	78 SEI	79 ADC abs,Y	7A NOP	7B ROR-ADC abs,Y	7C NOP abs	7D ADC abs,X	7E ROR abs,X	7F ROR-ADC abs,X

All instructions, including 'illegal' (unintentional side effects of the CPU's implementation)

00 BRK

01 ORA (zp,X)

02 HALT

03 ASL-ORA (zp,X)

04 NOP zp

05 ORA zp

06 ASL zp

07 ASL-ORA zp

08 PHP

09 ORA #n

0A ASL A

0B AND #n/MOV b7->Cy

0C NOP abs

0D ORA abs

0E ASL abs

0F ASL-ORA abs

10 BPL rel

11 ORA (zp),Y

12 HALT

13 ASL-ORA (zp),Y

14 NOP zp

15 ORA zp,X

16 ASL zp,X

17 ASL-ORA abs,X

18 CLC

19 ORA abs,Y

1A NOP

1B ASL-ORA abs,Y

1C NOP abs

1D ORA abs,X

1E ASL abs,X

1F ASL-ORA abs,X

20 JSR abs

21 AND (zp,X)

22 HALT

23 ROL-AND (zp,X)

24 BIT zp

25 AND zp

26 ROL zp

27 ROL-AND zp

28 PLP

29 AND #n

2A ROL A

2B AND #n-MOV b7->Cy

2C BIT abs

2D AND abs

2E ROL abs

2F ROL-AND abs

30 BMI rel

31 AND (zp),Y

32 HALT

33 ROL-AND (zp),Y

34 NOP zp

35 AND zp,X

36 ROL zp,X

37 ROL-AND zp,X

38 SEC

39 AND abs,Y

3A NOP

3B ROL-AND abs,Y

3C NOP abs

3D AND abs,X

3E ROL abs,X

3F ROL-AND abs,X

40 RTI

41 EOR (zp,X)

42 HALT

43 LSR-EOR (zp,X)

44 NOP zp

45 EOR zp

46 LSR zp

47 LSR-EOR zp

48 PHA

49 EOR #n

4A LSR A

4B AND #n-LSR A

4C JMP abs

4D EOR abs

4E LSR abs

4F LSR-EOR abs

50 BVC rel

51 EOR (zp),Y

52 HALT

53 LSR-EOR (zp),Y

54 NOP zp

55 EOR zp,X

56 LSR zp,X

57 LSR-EOR abs,X

58 CLI

59 EOR abs,Y

5A NOP

5B LSR-EOR abs,Y

5C NOP abs

5D EOR abs,X

5E LSR abs,X

5F LSR-EOR abs,X

60 RTS

61 ADC (zp,X)

62 HALT

63 ROR-ADC (zp,X)

64 NOP zp

65 ADC zp

66 ROR zp

67 ROR-ADC zp

68 PLA

69 ADC #n

6A ROR A

6B AND #n-ROR A

6C JMP (abs)

6D ADC abs

6E ROR abs

6F ROR-ADC abs

70 BVS rel

71 ADC (zp),Y

72 HALT

73 ROR-ADC (zp),Y

74 NOP zp

75 ADC zp,X

76 ROR zp,X

77 ROR-ADC abs,X

78 SEI

79 ADC abs,Y

7A NOP

7B ROR-ADC abs,Y

7C NOP abs

7D ADC abs,X

7E ROR abs,X

7F ROR-ADC abs,X

80 NOP zp

81 STA (zp,X)

82 HALT

83 STA-STX (zp,X)

84 STY zp

85 STA zp

86 STX zp

87 STA-STX zp

88 DEY

89 NOP zp

8A TXA

8B TXA-AND #n

8C STY abs

8D STA abs

8E STX abs

8F STA-STX abs

90 BCC rel

91 STA (zp),Y

92 HALT

93 STA-STX (zp),Y

94 STY zp,X

95 STA zp,X

96 STX zp,Y

97 STA-STX zp,Y

98 TYA

99 STA abs,Y

9A TXS

9B STA-STX abs,Y

9C STA-STX abs,X

9D STA abs,X

9E STA-STX abs,X

9F STA-STX abs,X

A0 LDY #n

A1 LDA (zp,X)

A2 LDX #n

A3 LDA-LDX (zp,X)

A4 LDY zp

A5 LDA zp

A6 LDX zp

A7 LDA-LDX zp

A8 TAY

A9 LDA #n

AA TAX

AB LDA-LDX

AC LDY abs

AD LDA abs

AE LDX abs

AF LDA-LDX abs

B0 BCS rel

B1 LDA (zp),Y

B2 HALT

B3 LDA-LDX (zp),Y

B4 LDY zp,X

B5 LDA zp,X

B6 LDX zp,Y

B7 LDA-LDX zp,Y

B8 CLV

B9 LDA abs,Y

BA TSX

BB LDA-LDX abs,Y

BC LDY abs,X

BD LDA abs,X

BE LDX abs,Y

BF LDA-LDX abs,Y

C0 CPY #n

C1 CMP (zp,X)

C2 HALT

C3 DEC-CMP (zp,X)

C4 CPY zp

C5 CMP zp

C6 DEC zp

C7 DEC-CMP zp

C8 INY

C9 CMP #n

CA DEX

CB SBX #n

CC CPY abs

CD CMP abs

CE DEC abs

CF DEC-CMP abs

D0 BNE rel

D1 CMP (zp),Y

D2 HALT

D3 DEC-CMP (zp),Y

D4 NOP zp

D5 CMP zp,X

D6 DEC zp,X

D7 DEC-CMP zp,X

D8 CLD

D9 CMP abs,Y

DA NOP

DB DEC-CMP abs,Y

DC NOP abs

DD CMP abs,X

DE DEC abs,X

DF DEC-CMP abs,X

E0 CPX #n

E1 SBC (zp,X)

E2 HALT

E3 INC-SBC (zp,X)

E4 CPX zp

E5 SBC zp

E6 INC zp

E7 INC-SBC zp

E8 INX

E9 SBC #n

EA NOP

EB SBC #n

EC CPX abs

ED SBC abs

EE INC abs

EF INC-SBC abs

F0 BEQ rel

F1 SBC (zp),Y

F2 HALT

F3 INC-SBC (zp),Y

F4 NOP zp

F5 SBC zp,X

F6 INC zp,X

F7 INC-SBC zp,X

F8 SED

F9 SBC abs,Y

FA NOP

FB INC-SBC abs,Y

FC NOP abs

FD SBC abs,X

FE INC abs,X

FF INC-SBC abs,X